1. Field of the Invention
This invention generally relates to methods and a system for processing a microelectronic topography, particularly for processes associated with an electroless deposition process.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Electroless plating is a process for depositing materials on a catalytic surface from an electrolyte solution without an external source of current. An advantage of an electroless deposition process is that it can be selective, i.e., the material can be deposited only onto areas that demonstrate appropriate chemical properties. In particular, local deposition can be performed onto metals that exhibit an affinity to the material being deposited or onto areas pretreated or pre-activated, e.g., with a catalyst. The material or catalyst applied onto the selected areas is sometimes called a “seed material” or “seed layer” and the ratio of the deposition rate on the activated regions to the deposition rate at the non-activated regions is known as the “deposition process selectivity.” For many applications, it is important to provide a deposition of high selectivity. Other important characteristics of an electroless deposition process are uniform thickness and adherence of the deposited layer to the substrate.
Most conventional electroless deposition processes include a series of solution baths. Such a series of baths are used for preparing a surface for the electroless deposition process, as well as the processes including and subsequent to the deposition process. Such a process configuration, however, facilitates the deposition of foreign particles and/or contaminants on a substrate surface when transferring the substrates from bath to bath. Another common problem with treating a surface in a series of baths is the exposure of the substrate surface to air during the transfer between baths. Such an exposure to air may cause oxidation of the substrate surface that will result in poor catalytic activity and poor quality metal deposits. This problem becomes especially troublesome when using materials that easily oxidize in air, such as copper. In an attempt to overcome these problems, some equipment manufacturers have proposed apparatuses which process a substrate in one chamber for a plurality of different process steps associated with an electroless deposition process.
Such apparatuses, however, fail to prevent the solutions from the plurality of different process steps from mixing once they are expelled from the process chamber. Consequently, the apparatuses may not reuse process solutions within the apparatus, incurring higher material costs and waste disposal costs for the electroless deposition process. In addition, such apparatuses fail to provide a manner with which to supply air exterior to the process chamber during processing, such as for a drying step, for example. In particular, prior art apparatuses may only offer two modes of operation, one in which the chamber is sealed for processing and another in which the chamber is not sealed for loading. In other cases, prior art apparatuses may not be sealed at all. In any embodiment, another problem with conventional process chambers is the manner in which a substrate is secured within the process chamber. In particular, few conventional process chambers offer a manner with which to secure a substrate without causing damage to the substrate, particularly along the edges of the substrate.
One common drawback of existing electroless deposition processes and apparatuses is low speed of deposition. For example, a typical electroless deposition process does not generally exceed 100 nm/min. The deposition rate of an electroless process may generally depend on the material to be deposited and, therefore, the deposition rate may be much lower than 100 nm/min, in some cases. For example, the speed of deposition of a cobalt-tungsten-phosphorus layer may be within between approximately 0.01 nm/min and approximately 10 nm/min. In general, the deposition rate of an electroless process may depend on characteristics of the activated areas, such as dimensions, profiles of the exposed surfaces, and distances between the portions of the areas to be activated. In some embodiments, the deposition rate of an electroless process may further depend on the temperature of the solution used to deposit the material. In particular, the deposition rate may increase with increases in temperature. However, many electroless deposition solutions tend to decompose at high temperatures, leading to significant non-uniformities in the deposited material. On the other hand, deposition rates of electroless solutions at relatively low temperatures may be undesirably low, reducing production throughput and increasing fabrication costs.
Another common problem with electroless deposition processes is the formation of gas bubbles on the substrate surface during processing. In general, the formation of gas bubbles may be due to the evolution of hydrogen during the reduction-oxidation process of the electroless deposition process and/or by a high level of hydrophobicity within the substrate of the wafer. The gas bubbles undesirably prevent a material from being deposited uniformly upon a substrate surface, potentially depositing a layer outside the specifications of the process.
In some embodiments, electroless deposition may be used for the formation of metal features within integrated circuits. In fact, electroless deposition techniques may be particularly advantageous for forming copper features within a microelectronic topography, which well matches the present trend for using copper as interconnect materials instead of aluminum, tungsten, silicides, or the like. In addition, electroless deposition techniques are favorable for depositing materials into deep holes within the topography that cannot be uniformly covered by other deposition techniques, such as sputtering and evaporation, for example. As such, an electroless deposition process may be advantageous for depositing a metal material using a dual damascene process.
In some microelectronic devices, a trench comprising a metal feature may also include a liner layer and a cap layer to prevent the diffusion of the bulk metal layer within the metal feature to underlying and overlying layers of the topography, respectively. In some cases, however, it may be difficult to clean and activate the barrier layer for a sufficient deposition of a bulk metal layer. In particular, the barrier layer may be cleaned and activated for the deposition of the bulk metal layer, but it may be difficult to prevent the surface from being contaminated between processes. In addition or alternatively, it may be difficult to selectively deposit or align a cap layer upon the bulk metal layer such that no other metal adheres to the dielectric portions of the topography arranged adjacent to the metal feature. In embodiments in which a bulk metal layer is polished to be confined within the sidewalls of a trench, the dielectric portion of the topography arranged adjacent to the metal feature may include small fragments of the bulk metal layer upon its upper surface. The small fragments may be catalytic to the electroless deposition of the cap layer or may attract a catalytic seed layer used to electrolessly deposit the cap layer. In either case, portions of the cap layer may be undesirably deposited upon the dielectric portion, potentially causing a short within the circuit.
As such, it would be advantageous to develop a system and methods for processing a microelectronic topography, particularly for processes associated with an electroless deposition process. For example, it would be desirable to develop a system which is configured to conduct one or more process steps within a chamber without taking a microelectronic topography arranged therein out between steps. In addition, it would be beneficial to have a system which prevents process solutions from mixing upon being dispensed from the process chamber. Such a process chamber may be further adapted to secure a wafer within the chamber as well as have a means to provide an air passage to the chamber during processing. In some cases, the process chamber may be additionally or alternatively adapted to prevent the generation and accumulation of bubbles upon a wafer surface during processing. In addition, the process chamber may be configured to offer a manner with which to increase the boiling point of an electroless deposition solution used within the chamber. Additional benefits may also be realized by methods which offer to provide a barrier layer which is not contaminated by particles prior to an electroless deposition process and which is either autocatalytic or is readily available for the deposition of a catalytic seed layer. In addition, it may be advantageous to develop a method which prevents the deposition of a cap layer upon dielectric portions of a topography.